They are named as proc_sys_reset_2 and proc_sys_reset_3 by default.Ĭlick Run Connection Automation, which will open a dialog that will help connect the proc_sys_reset blocks to the clocking wizard clock outputs.Įnable All Automation on the left side of the Run Connection Automation dialog box. Select the proc_sys_reset_1 block, type Ctrl-C and Ctrl-V to replicate two modules. Rename the reset block to proc_sys_reset_1 so that it’s easy to understand the relationship between reset modules and the clock signals. Search for and add a Processor System Reset from the IP Search dialog Before that, we need to create reset signals for each clock because they are needed in clock export setup.Īdd three Processor System Reset blocks corresponging to the three clocks: We’ll setup the clock export in future steps. You are free to modify the clock quantities and frequency to fit your target design. 200MHz and 400MHz clocks are reserved for DPU AXI interface clock and DPU core clock during design linking phase. In this simple design, we would use 100MHz clock as the axi_lite control bus clock. This clock wizard uses the pl_clk as input clock and generates clocks needed for the whole logic design. Note: So now we have set up the clock system for our design. Set the Requested Output Freq as follows:Īt the bottom of the dialog box set the Reset Type to Active Low. Search for and add a Clocking Wizard from the IP Search dialog.ĭouble-click the clk_wiz_0 IP block to open the Re-Customize IP dialog box.Įnable clk_out1 through clk_out3 in the Output Clock column. Here are the detailed steps.Īdd the clocking wizard block to generate three clocks: We will add the Clocking Wizard to the block diagram and enable clock signals for the platform. To provide more interrupt signals, or to provide phase aligned clocks, we can use Clocking Wizard. The limitation is that the processor has maximum 4 pl_clks and their phase is not aligned. The available clock signals in the platform are exported by PFM.CLK property.įor simple designs, interrupt signals can be sourced by processor’s pl_clk. V++ linker can automatically link the clock signals between kernel and platform. Next we’ll add the IP blocks and metadata to create a base hardware design that supports acceleration kernels.Ĭustomize System Design for Clock and Reset ¶ The presets includes MPSoC PS block configurations and pin assignments.įor a custom board, please double click MPSoC block and setup parameters according to the board hardware. You should get MPSoC block configured like below:Īt this stage, the Vivado block automation has added a Zynq UltraScale+ MPSoC block and applied all board presets for the ZCU104. In the Run Block Automation dialog, ensure the following is check marked:Ĭlick OK. Search for zynq and then double-click the Zynq UltraScale+ MPSoC from the IP search results.Ĭlick the Run Block Automation link to apply the board presets. Right click Diagram view and select Add IP. (Optional) Change the design name to system.Īdd MPSoC IP and run block automation to configure it. In Project Manager, under IP INTEGRATOR, select Create Block Design. Note: If you need to change an existing Vivado project to an extensible platform project, you can go to Settings in Flow Navigator in an opened Vivado design, go to General and enable project is an extensible Vitis platform Select Boards tab and then select Zynq UltraScale+ ZCU104 Evaluation Board. Click Next.Įnable Project is an extensible Vitis platform. In Project Name dialog set Project name to zcu104_custom_platform. Create a Vivado project named zcu104_custom_platform.
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